As will be appreciated by those skilled in the art, in reading and writing data from and into an SRAM array at high speed, the relative arrival and set up time of various signals that provide access to the array is can be limiting factor in the overall speed of operation of the array. At the state of the art speed of SRAM operation, there is an inherent range of arrival and set up times of the data and address signals for which allowance must be made.
FIG. 1 is a functional block diagram of a state of the art prior art SRAM macro. The Memory Array has boundary L1/L2 latches at its address input (ADDR) and at its data output (Data Out_q). For application flexibility, the array also provides an unlatched output labeled Data Out. These inputs and output are fully static. The boundary latches are controlled by a normal Local Clock Buffer (nLCB) clock signal generated from the system clock nclk. The nLCB generates d1clk and lclk clocks to control respectively the L1 and L2 race-free boundary latches. An array Local Clock Buffer (array LCB) generates from the system clock nclk a local clock signal aclk for internal array circuit timing control. Both the nLCB and array LCB are programmable to provide timing adjustments on leading edge, trailing edge, and pulse width (PW) of the local clocks. This programmable control is provided by the GPTR (General Purpose Test Register) scannable latches. Each LCB has its own set of GPTR latches so that it could be programmed independently. As shown in FIG. 1, the address latches, data-in latches, and data_out latches all have their own nLCB. The array bit decode path, the word decode path (WD lsb, or least significant bit, and WD msb, or most significant bit), and the read/write decode path (RW Dec) each also has separated array LCB. This scheme of macro internal clocking topology provides maximum circuit timing control flexibility for performance optimization and hardware debug capability. The nominal timing sequence of the array inputs and the control clocks are illustrated in FIG. 5.
Referring to FIGS. 1 and 5, a brief description of the SRAM functional blocks and operational sequence are now given. The array macro inputs (address, data-in, read/write control) have boundary L1/L2 latches. At the beginning of a cycle when nclk falls, d1clk from the nLCB is driven low to close (hold state) the boundary L1 latches, and the lclk is driven high to open (flush state) the boundary L2 latches. With d1clk falling and lclk rising, the inputs are captured and held in the L1 and L2 latches. Output from the L1 or L2 latches are then sent to subsequent array peripheral circuits for decoding and read/write control function. When nclk falls, aclk from the array LCB is driven high to activate the dynamic bit, word, and read/write decode circuits. Dynamic circuits are typically used in state of the art high performance SRAMs because of their faster switching time. Static signals from the L1 latches shown in FIG. 1 must arrive at these dynamic circuits before the aclk is activated. In the word selection path, two levels of word decode is illustrated in the FIG. 1 SRAM functional block diagram. Level 1 consists of the lsb (least significant bits) and msb (most significant bits) Word Decoders (WD). Level 2 is performed by the WL Dec Drv (Word Line Decode and Drive) block. A selected wordline's (WL) leading edge (rising transition) is triggered by the leading edge of aclk, and its trailing edge (falling transition) is controlled by the aclk falling. The selected WL's active window is therefore determined by the aclk's active pulse width (PW). Similarly as shown in the timing diagram, the dynamic WE (Write Enable) signal also resembles that of the WL. The WE signal is driven off from the RW Dec/Drv (Read Write Decode/Drive) block and is used to generate dynamic true/complement write data (wt/wc) from the static data L1/L2 latch to write the Memory Array.
For a read or write-through operation, after a wordline and a bit column is selected (a bit column is selected by the Bit Dec and Column decode/select blocks), read or write-through data from the Memory Array is then passed to the array output driver.
For an array write operation, data-in for writing is captured and sent off by the data-in L1/L2 latches. The static data from the L1/L2 latches (dt and dc signals as shown in FIG. 5 timing diagram) must arrive at the Read/Write Control block before the dynamic WE or WL signals arrive to start the Memory Array's read/write operation. This data setup time requirement is denoted by the “ts” time in the timing diagram. The static data dt/dc must also be held stable for the full duration of the WL/WE active window in order to guarantee a successful write operation. This hold time requirement is denoted by the “ts” time in the timing diagram.
FIG. 2 is one prior art implementation of a data input latch used in the macro shown in FIG. 1. In this implementation, the data input to the L1 stage is clocked into that stage in response to the leading edge of the d1clk signal generated by the local clock buffer nLCB in response to the system clock signal nclk. The output of the L1 stage is latched into the L2 stage in response to the lclk clock leading (rising) edge, which is also generated by the nLCB. One drawback is that the parameters that determine the timing of the launch of the data from the L2 necessarily have a range of values. This can result in a late launch of the L2 data so that the data at the input to the memory array does not have the set up time required by the memory array. This will cause a slower write performance, degrading the SRAM macro's overall cycle time capability. An additional drawback is the chip area and power required for both an L1 and an L2 latches.
FIG. 3 is a data input latch similar to FIG. 2, but using only an L1 latch to latch and launch the input data. This allows a fast launch of the input data from the L1 latch with a static input that supports fast cycle times. However, the early launch of the L1 data in the middle of a high frequency memory cycle, gives rise to the possibility that the data will arrive before the current write operation time window expires; referred to in the art as an early mode issue. It will be appreciated that early mode problems arise also if the ackl clock signal is delayed with respect to its designed timing, or the pulse width PW of the aclk is wider than the design pulse width. The aclk delay or PW is programmable by the array LCB and will be altered as needed during hardware debug and characterization. It is essential to avoid this potential early mode problem cause by internal aclk timing adjustments.